In the fabrication of a printed circuit board (PCB) it is desirable to provide electrical connection of circuits at various layers within the PCB. This is typically done using a plated through hole (PTH). A PTH is typically formed using the steps of drilling, desmearing, and plating. The hole quality before plating has an impact on the robustness of the finished PTH, particularly its ability to withstand thermal cycling, such as through multiple high temperature solder reflows, without fatiguing to the point of failure.
A PCB is normally made of layers of conductive and dielectric material. The conductive material is typically metal, such as copper, and the dielectric material is typically an organic polymer. The layers may be adhered using a bonding agent, typically a prepreg sheet adhesive. In forming the PTH, holes are drilled through the conductive material and the dielectric material using a mechanical drill bit, or in some cases a laser. There are several variables in the drilling process which can affect the hole roughness. The drill bit design, the drill bit sharpness, the insulating dielectric material being drilled in the PCB insulating layers, the rotation of the drill bit (speed) and the rate at which the drill bit is forced down through the PCB (feed) all can play a role in the hole roughness.
When drilling the holes using a drill bit, heat from friction commonly causes organic materials from the insulating material and the bonding agents to coat the inner hole surface, at least partially coating exposed surfaces of the conductive material. The coating is removed prior to plating to provide an electrical connection between the plating material and the conductive material of the PCB. A desmear process is used after drilling the hole to remove the polymer coating. A typical desmear process consists of swelling the resin with an organic solvent, etching the resin with a hot alkaline potassium permanganate solution, and neutralizing the alkaline permanganate with an acid such as sulfuric acid. Various parameters such as swelling and etching time and temperature and permanganate concentration can affect the dielectric etching. If the etching is not aggressive enough, smear will remain on the inner hole surface and can result in a poor electrical and mechanical connection when the PTH is plated. If the etch is too aggressive, the dielectric layers can be etched excessively, resulting in recesses in the hole surface between the conductive layers, leading to excessive hole roughness that can cause defects.
Following desmear, the PTH is plated, typically with copper. A variety of plating processes can be used, such as full panel plate or pattern plate. A typical plating process involves applying a seed layer in the hole, such as colloidal palladium. An electroless copper bath is used to deposit a layer of copper thick enough to carry some current, then the PCB is plated in an electrolytic copper bath. Since the plating follows the topography of the PTH sidewall, the roughness of the copper plating is influenced by the roughness of the sidewall prior to plating.
The PTH reliability is strongly influenced by the sidewall roughness, and to minimize roughness the drill, desmear, and plating operations are commonly co-optimized to achieve the best results. Standard practice is to experimentally vary the drill, desmear, and plate parameters to find an optimum combination for a particular PCB design.
With the challenges described above, forming reliable PTHs in high aspect ratio PCBs is generally difficult. The PCBs can be from 3 mm to 10 mm thick, with typical aspect ratios ranging from 10:1 up to 15:1 for thicker panels. As demand for device density on PCBs increases, the PCB industry is gradually decreasing via wall-to-wall distances between PTHs and size of PTHs. This trend increases the likelihood of conductive anodic filament (CAF) formation, which is a failure mode characterized by formation of copper filaments in the PCB between adjacent conductive layers or PTHs leading to short circuits in the PCB. Therefore, there is a need to improve PCB reliability by mitigating the likelihood of CAF formation within the PCB multilayer structure.
There is also a need in the art to mitigate PTH wall roughness, which is a known contributor to PTH failures. Rough side walls may result in degraded laminate integrity leading to insulation resistance failures in the dielectric and/or barrel cracks in the PTH plating. Hole wall roughness is known to cause stress risers to grow in the copper plating, leading to reduced connectivity and laminate adhesion in the PCB and the PTH.